Bulk finFET devices can be fabricated for complementary metal-oxide-semiconductor (CMOS) technologies, particularly at the 22 nm node and beyond. The bulk finFET devices can be used in a variety of applications such as microprocessors, microcontrollers, and other digital logic circuits. N-well and P-well contacts are typically used in the layout of bulk finFET devices to avoid latch-up and ensure adequate device-to-device isolation electrically. However, the contact regions of the N-well and P-well disrupt regular fin patterning, and thus degrade uniformity of the layout of the bulk finFET devices. The degradation in uniformity of the layout of the bulk finFET devices results in variable patterning and etching, and consequently electrical degradation.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.